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Integrated Circuit Systems, Inc.
ICS93705
DDR Phase Lock Loop Zero Delay Clock Buffer
Recommended Application: DDR Zero Delay Clock Buffer Product Description/Features: * Low skew, low jitter PLL clock driver * I2C for functional and output control * Feedback pins for input to output synchronization * Spread Spectrum tolerant inputs * 3.3V tolerant CLK_INT input Switching Characteristics: * PEAK - PEAK jitter (66MHz): <120ps * PEAK - PEAK jitter (>100MHz): <75ps * CYCLE - CYCLE jitter (66MHz):<120ps * CYCLE - CYCLE jitter (>100MHz):<65ps * OUTPUT - OUTPUT skew: <100ps * Output Rise and Fall Time: 450ps - 950ps * DUTY CYCLE: 49% - 51%
GND CLKC0 CLKT0 VDD CLKT1 CLKC1 GND GND CLKC2 CLKT2 VDD SCLK CLK_INT N/C VDD AVDD AGND GND CLKC3 CLKT3 VDD CLKT4 CLKC4 GND
Pin Configuration
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND CLKC5 CLKT5 VDD CLKT6 CLKC6 GND GND CLKC7 CLKT7 VDD SDATA N/C FB_INT VDD FB_OUTT N/C GND CLKC8 CLKT8 VDD CLKT9 CLKC9 GND
48-Pin SSOP
Block Diagram
FB_OUTT CLKT0 CLKC0 CLKT1 CLKC1
Functionality
INPUTS AVDD CLK_INT 2.5V (nom) 2.5V (nom) L H OUTPUTS CLKT CLKC FB_OUTT L H Z L H H L Z H L L H Z L H PLL State on on off Bypassed/off Bypassed/off
SCLK SDATA
Control Logic
CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 CLKT5 CLKC5
2.5V <20MHz(1) (nom) GND GND L H
FB_INT CLK_INT
PLL
CLKT6 CLKC6 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9
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ICS93705
ICS93705
Pin Descriptions
PIN NUMBER PIN NAME TYPE PWR OUT OUT PWR IN IN PWR PWR OUT IN I/O Ground "Complementary" clocks of differential pair outputs. "Tr ue" Clock of differential pair outputs. Power supply 2.5V Clock input of I2C input, 5V tolerant input "True" reference clock input, 3.3V tolerant input Not connected Analog power supply, 2.5V A n a l o g gr o u n d . "True" Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INT. "True" Feedback input, provides feedback signal to the internal PLL for synchronization with CLK_INT to eliminate phase error. Data pin for I2C circuitry 5V tolerant DESCRIPTION
1, 7, 8, 18, 24, 25, GND 31, 41, 42, 48 26, 30, 40, 43, 47, CLKC(9:0) 23, 19, 9, 6, 2 27, 29, 39, 44, 46, CLKT(9:0) 22, 20, 10, 5, 3 4, 11, 15, 21, 28, 34, 38, 45, 12 13 14, 32, 36 16 17 33 35 37 VDD SCLK CLK_INT N/C AVDD AGND FB_OUTT FB_INT SDATA
Byte 0: Output Control (1= enable, 0 = disable)
Byte 1: Output Control (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# -
PWD 1 1 1 1 1 1 1 1
DESCRIPTION Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# -
PWD 1 1 1 1 1 1 1 1
DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
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ICS93705
Byte 2: Reserved (1= enable, 0 = disable)
Byte 3: Reserved (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# -
PWD 1 1 1 1 1 1 1 1
DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
BIT PIN# PWD Bit 7 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 1 Bit 0 1
DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Byte 4: Reserved (1= enable, 0 = disable) BIT PIN# PWD DESCRIPTION Bit 7 1 Reserved Bit 6 1 Reserved Bit 5 1 Reserved Bit 4 1 Reserved Bit 3 1 Reserved Bit 2 1 Reserved Bit 1 1 Reserved Bit 0 1 Reserved
Byte 5: Reserved (1= enable, 0 = disable)
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# PWD 3,2 1 1 10, 9 1 20, 19 1 22, 23 1 27, 26 1 1 1
DESCRIPTION CLK0 (T&C) CLK2 (T&C) CLK3 (T&C) CLK4 (T&C) CLK9 (T&C) Reser ved Reser ved
Byte 6: Reserved (1= enable, 0 = disable)
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# PWD 0 0 0 29, 30 1 39, 40 1 44, 43 1 46, 47 1 1
DESCRIPTION Reser ved (Note) Reser ved (Note) Reser ved (Note) CLK8 (T&C) CLK7 (T&C) CLK6 (T&C) CLK5 (T&C) Reser ved
Note: Don't write into these registers (7:5), writing into these registers can cause malfunction.
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ICS93705
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD) . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . -0.5V to 3.6V GND -0.5 V to VDD +0.5 V 0C to +85C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input / Supply / Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 2.5 V +/-0.2V (unless otherwise stated) PARAMETER Input High Current Input Low Current Operating Supply Current Output High Current Output High Current High Impedance Output Current Input Clamp Voltage High-level Output Voltage Low-level Output Voltage Input Capacitance
1 1 1
SYMBOL IIH IIL IDD2.5 IDDPD I OH I OL I OZ VIK VOH VOL CIN COUT
CONDITIONS VI = VDD or GND VI = VDD or GND CL = 0 pF at 133 MHz CL = 0 pF VDD = 2.3V, VOUT = 1V VDD = 2.3V, VOUT = 1.2V VDD = 2.7V, VOUT = VDD or GND Iin = -18 mA; VDD = min to max, IOH = -1mA VDD = 2.3V, I OH = -12mA VDD = min to max, IOH = 1mA VDD = 2.3V, I OH = 12mA VI = VDD or GND VI = VDD or GND
MIN
TYP
MAX
UNITS A A
245 -43 26 43
300 100 -18
mA A mA mA
10
A V
2.1
2.42 1.87 0.04 0.35 3 0.1 0.6
V V V V pF pF
Output Capacitance
Guaranteed by design, not 100% tested in production.
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ICS93705
Recommended Operating Condition
TA = 0 - 70C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER Analog/core supply voltage Input voltage level Input duty cycle Input max jitter SYMBOL VDD, A VDD VIL VIH IDC ITCYC CONDITIONS MIN 2.3 VDD/2 + 0.5V 40 TYP 2.5 MAX 2.7 VDD/2 - 0.5V 60 500 UNITS V V V % ps
Timing Requirements
TA = 0 - 70C; Supply Voltage AVDD, VDD = 2.5 V +/-0.2V (unless otherwise stated) PARAMETER Operating Clock Frequency Input Clock Duty Cycle Clock Stabilization
1 1 1
SYMBOL freq op d tin t STAB
CONDITIONS
MIN 66 40
TYP
MAX 170 60 100
UNITS MHz % s
from VDD = 2.5V to 1% target frequency
1. Guaranteed by design, not 100% tested in production.
Switching Characteristics
TA = 0 - 70C; Supply Voltage VDD = 2.5 V +/-0.2V (unless otherwise stated) PARAMETER Absolute Jitter1 Cycle to cycle Jitter1,2 Phase Error1 Output to output Skew
1
SYMBOL t jabs t c-c t pe Tskew t PLH Tskewp
1,3
CONDITIONS 66 MHz 100 / 125 / 133 / 167 MHz 66 MHz 100 / 125 / 133 / 167 MHz with input clock 0-2.5V 0.8ns rise/fall with input clock 0-2.5V 0.8ns rise/fall CLK_IN to any output, Load = 120W / 12 pF
MIN
TYP
MAX 120 75
UNITS ps ps ps ps ns ps % ps
50 35 -150 50 40 4 4.5
110 65 150 100 6 100
Low-to-high level Propagation Delay Time, Bypass Mode1 Pulse Skew1 Duty Cycle (differential) Rise Time, Fall Time
1
DC t R, t F
no loads, 66 MHz to 167 MHz Single-ended 20 - 80 %; Load = 120 / 12 pF
49 450
50 550
51 950
1. Guaranteed by design, not 100% tested in production. 2. Refers to transistion on non-inverting period. 3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = twH / t C, where the cycle time (t C) decreases as the frequency increases.
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ICS93705
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D4 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 6 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit
How to Write:
Controller (Host) Start Bit Address D4(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Stop Bit ICS (Slave/Receiver)
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D5 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
* * * * * * * *
How to Read:
Controller (Host) Start Bit Address D5(H) ICS (Slave/Receiver)
ACK
ACK Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS93705
N
c
SYMBOL
L
In Millimeters COMMON DIMENSIONS MIN MAX 2.413 0.203 0.203 2.794 0.406 0.343
In Inches COMMON DIMENSIONS MIN MAX .095 .008 .008 .110 .016 .0135
E1 INDEX AREA
E
A A1 b c
12 h x 45 D
D
0.127 0.254 SEE VARIATIONS 10.033 7.391 0.381 10.668 7.595 0.635
.005 .010 SEE VARIATIONS .395 .291 .015 .420 .299 .025
E E1 e h L N
0.635 BASIC 0.508 1.016 SEE VARIATIONS 0 8
0.025 BASIC .020 .040 SEE VARIATIONS 0 8
A A1
-Ce
b SEATING PLANE .10 (.004) C
VARIATIONS N 48
D mm. MIN 15.748 MAX 16.002 MIN .620
D (inch) MAX .630
6/ 1/ 00 REV B
300 mil SSOP
JEDEC MO- 118 DOC# 10- 0034
Ordering Information
ICS93705yF-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
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